Conventional direct digital synthesizers (DDS) usually comprise at least a high speed clock, a programmable shift register and an N-bit accumulator which includes a carry out output. The carry out output signal from the synthesizer has an average frequency (Fo) equal to the clock frequency (Fc) divided by the accumulator length (2.sup.n) times the phase increment value (program value, P). The relationship can be stated mathematically as: EQU F.sub.o =(F.sub.c /2.sup.n)*P
where Fc/2.sup.n defines the resolution of the frequency output. For example, if we assume a clock frequency of 1 gigahertz and a accumulator having 32 bits the resolution can be calculated as: EQU 1 GHZ/2.sup.32 =0.2328 Hz.
A spectral analysis of a conventional DDS output signal would show that the output frequency Fo and its harmonics include sideband spurs (spurious emissions). These sideband spurs (or jitter) when viewed from a spectrum analyzer exhibit a pattern which resemble a Christmas-tree around each output frequency and their respective harmonics, at an offset frequency equal to the resolution of the accumulator, and also at harmonics of the offset frequencies. The sideband spur levels will vary according to the jitter pattern generated by the relationship of the value of "P" to the value of "2.sup.n " in the previously mentioned formula. These spurs typically make conventional DDS output signals unstable as low noise RF signal sources.
In DDS applications, where a sine wave or other periodic wave is generated, the amplitude quantization errors become highly correlated to the wave being generated, thus causing spurs to be generated along with the output signal. A need thus exists for a method and apparatus for minimizing the jitter in a direct digital synthesizer in order to provide for very low spurious output signals. This would in effect allow for a direct digital synthesizer to be used as a low spurious signal source for use in communication devices.